git.techno-innov.fr Git - elec/adapters/orangepi/blob - OPiZero2_Rack/OPiZero2_Rack.kicad_pro

   1 {
   2   "board": {
   3     "3dviewports": [],
   4     "design_settings": {
   5       "defaults": {
   6         "board_outline_line_width": 0.381,
   7         "copper_line_width": 0.381,
   8         "copper_text_italic": false,
   9         "copper_text_size_h": 1.524,
  10         "copper_text_size_v": 2.032,
  11         "copper_text_thickness": 0.30479999999999996,
  12         "copper_text_upright": false,
  13         "courtyard_line_width": 0.049999999999999996,
  14         "dimension_precision": 4,
  15         "dimension_units": 3,
  16         "dimensions": {
  17           "arrow_length": 1270000,
  18           "extension_offset": 500000,
  19           "keep_text_aligned": true,
  20           "suppress_zeroes": false,
  21           "text_position": 0,
  22           "units_format": 1
  23         },
  24         "fab_line_width": 0.09999999999999999,
  25         "fab_text_italic": false,
  26         "fab_text_size_h": 1.0,
  27         "fab_text_size_v": 1.0,
  28         "fab_text_thickness": 0.15,
  29         "fab_text_upright": false,
  30         "other_line_width": 0.09999999999999999,
  31         "other_text_italic": false,
  32         "other_text_size_h": 1.0,
  33         "other_text_size_v": 1.0,
  34         "other_text_thickness": 0.15,
  35         "other_text_upright": false,
  36         "pads": {
  37           "drill": 2.5,
  38           "height": 2.5,
  39           "width": 2.5
  40         },
  41         "silk_line_width": 0.22097999999999998,
  42         "silk_text_italic": false,
  43         "silk_text_size_h": 1.524,
  44         "silk_text_size_v": 1.524,
  45         "silk_text_thickness": 0.30479999999999996,
  46         "silk_text_upright": false,
  47         "zones": {
  48           "45_degree_only": false,
  49           "min_clearance": 0.15
  50         }
  51       },
  52       "diff_pair_dimensions": [
  53         {
  54           "gap": 0.0,
  55           "via_gap": 0.0,
  56           "width": 0.0
  57         }
  58       ],
  59       "drc_exclusions": [],
  60       "meta": {
  61         "filename": "board_design_settings.json",
  62         "version": 2
  63       },
  64       "rule_severities": {
  65         "annular_width": "error",
  66         "clearance": "error",
  67         "copper_edge_clearance": "error",
  68         "courtyards_overlap": "error",
  69         "diff_pair_gap_out_of_range": "error",
  70         "diff_pair_uncoupled_length_too_long": "error",
  71         "drill_out_of_range": "error",
  72         "duplicate_footprints": "warning",
  73         "extra_footprint": "warning",
  74         "footprint_type_mismatch": "error",
  75         "hole_clearance": "error",
  76         "hole_near_hole": "error",
  77         "invalid_outline": "error",
  78         "item_on_disabled_layer": "error",
  79         "items_not_allowed": "error",
  80         "length_out_of_range": "error",
  81         "malformed_courtyard": "error",
  82         "microvia_drill_out_of_range": "error",
  83         "missing_courtyard": "ignore",
  84         "missing_footprint": "warning",
  85         "net_conflict": "warning",
  86         "npth_inside_courtyard": "ignore",
  87         "padstack": "error",
  88         "pth_inside_courtyard": "ignore",
  89         "shorting_items": "error",
  90         "silk_over_copper": "warning",
  91         "silk_overlap": "warning",
  92         "skew_out_of_range": "error",
  93         "through_hole_pad_without_hole": "error",
  94         "too_many_vias": "error",
  95         "track_dangling": "warning",
  96         "track_width": "error",
  97         "tracks_crossing": "error",
  98         "unconnected_items": "error",
  99         "unresolved_variable": "error",
 100         "via_dangling": "warning",
 101         "zone_has_empty_net": "error",
 102         "zones_intersect": "error"
 103       },
 104       "rule_severitieslegacy_courtyards_overlap": true,
 105       "rule_severitieslegacy_no_courtyard_defined": false,
 106       "rules": {
 107         "allow_blind_buried_vias": false,
 108         "allow_microvias": false,
 109         "max_error": 0.005,
 110         "min_clearance": 0.0,
 111         "min_copper_edge_clearance": 0.09999999999999999,
 112         "min_hole_clearance": 0.0,
 113         "min_hole_to_hole": 0.25,
 114         "min_microvia_diameter": 0.508,
 115         "min_microvia_drill": 0.127,
 116         "min_silk_clearance": 0.0,
 117         "min_through_hole_diameter": 0.3,
 118         "min_track_width": 0.2032,
 119         "min_via_annular_width": 0.0,
 120         "min_via_diameter": 0.508,
 121         "use_height_for_length_calcs": true
 122       },
 123       "track_widths": [
 124         0.0
 125       ],
 126       "via_dimensions": [
 127         {
 128           "diameter": 0.0,
 129           "drill": 0.0
 130         }
 131       ],
 132       "zones_allow_external_fillets": false,
 133       "zones_use_no_outline": true
 134     },
 135     "layer_presets": [],
 136     "viewports": []
 137   },
 138   "boards": [],
 139   "cvpcb": {
 140     "equivalence_files": []
 141   },
 142   "erc": {
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 316     ],
 317     "rule_severities": {
 318       "bus_definition_conflict": "error",
 319       "bus_entry_needed": "error",
 320       "bus_to_bus_conflict": "error",
 321       "bus_to_net_conflict": "error",
 322       "conflicting_netclasses": "error",
 323       "different_unit_footprint": "error",
 324       "different_unit_net": "error",
 325       "duplicate_reference": "error",
 326       "duplicate_sheet_names": "error",
 327       "endpoint_off_grid": "warning",
 328       "extra_units": "error",
 329       "global_label_dangling": "warning",
 330       "hier_label_mismatch": "error",
 331       "label_dangling": "error",
 332       "lib_symbol_issues": "warning",
 333       "missing_bidi_pin": "warning",
 334       "missing_input_pin": "warning",
 335       "missing_power_pin": "error",
 336       "missing_unit": "warning",
 337       "multiple_net_names": "warning",
 338       "net_not_bus_member": "warning",
 339       "no_connect_connected": "warning",
 340       "no_connect_dangling": "warning",
 341       "pin_not_connected": "error",
 342       "pin_not_driven": "error",
 343       "pin_to_pin": "warning",
 344       "power_pin_not_driven": "error",
 345       "similar_labels": "warning",
 346       "simulation_model_issue": "ignore",
 347       "unannotated": "error",
 348       "unit_value_mismatch": "error",
 349       "unresolved_variable": "error",
 350       "wire_dangling": "error"
 351     }
 352   },
 353   "libraries": {
 354     "pinned_footprint_libs": [],
 355     "pinned_symbol_libs": []
 356   },
 357   "meta": {
 358     "filename": "OPiZero2_Rack.kicad_pro",
 359     "version": 1
 360   },
 361   "net_settings": {
 362     "classes": [
 363       {
 364         "bus_width": 12,
 365         "clearance": 0.185,
 366         "diff_pair_gap": 0.25,
 367         "diff_pair_via_gap": 0.25,
 368         "diff_pair_width": 0.25,
 369         "line_style": 0,
 370         "microvia_diameter": 0.508,
 371         "microvia_drill": 0.127,
 372         "name": "Default",
 373         "pcb_color": "rgba(0, 0, 0, 0.000)",
 374         "schematic_color": "rgba(0, 0, 0, 0.000)",
 375         "track_width": 0.2032,
 376         "via_diameter": 0.508,
 377         "via_drill": 0.3,
 378         "wire_width": 6
 379       },
 380       {
 381         "bus_width": 12,
 382         "clearance": 0.19304,
 383         "diff_pair_gap": 0.25,
 384         "diff_pair_via_gap": 0.25,
 385         "diff_pair_width": 0.25,
 386         "line_style": 0,
 387         "microvia_diameter": 0.508,
 388         "microvia_drill": 0.127,
 389         "name": "HighPower",
 390         "pcb_color": "rgba(0, 0, 0, 0.000)",
 391         "schematic_color": "rgba(0, 0, 0, 0.000)",
 392         "track_width": 0.508,
 393         "via_diameter": 1.0,
 394         "via_drill": 0.5,
 395         "wire_width": 6
 396       },
 397       {
 398         "bus_width": 12,
 399         "clearance": 0.19304,
 400         "diff_pair_gap": 0.25,
 401         "diff_pair_via_gap": 0.25,
 402         "diff_pair_width": 0.25,
 403         "line_style": 0,
 404         "microvia_diameter": 0.508,
 405         "microvia_drill": 0.127,
 406         "name": "Power",
 407         "pcb_color": "rgba(0, 0, 0, 0.000)",
 408         "schematic_color": "rgba(0, 0, 0, 0.000)",
 409         "track_width": 0.3,
 410         "via_diameter": 0.508,
 411         "via_drill": 0.3,
 412         "wire_width": 6
 413       }
 414     ],
 415     "meta": {
 416       "version": 3
 417     },
 418     "net_colors": null,
 419     "netclass_assignments": null,
 420     "netclass_patterns": [
 421       {
 422         "netclass": "Power",
 423         "pattern": "+3.3V"
 424       },
 425       {
 426         "netclass": "Power",
 427         "pattern": "+5C"
 428       },
 429       {
 430         "netclass": "Power",
 431         "pattern": "+VCC"
 432       },
 433       {
 434         "netclass": "Power",
 435         "pattern": "+VCC3"
 436       },
 437       {
 438         "netclass": "Power",
 439         "pattern": "/5VDebug"
 440       },
 441       {
 442         "netclass": "Power",
 443         "pattern": "/5VInd"
 444       },
 445       {
 446         "netclass": "Power",
 447         "pattern": "/CMD_FAN"
 448       },
 449       {
 450         "netclass": "Power",
 451         "pattern": "/CMD_FAN_Filt"
 452       },
 453       {
 454         "netclass": "Power",
 455         "pattern": "/Ch1"
 456       },
 457       {
 458         "netclass": "Power",
 459         "pattern": "/Ch2"
 460       },
 461       {
 462         "netclass": "Power",
 463         "pattern": "/Ch3"
 464       },
 465       {
 466         "netclass": "Power",
 467         "pattern": "/USBVio_Dbg"
 468       },
 469       {
 470         "netclass": "Power",
 471         "pattern": "/USB_5VFilt_Dbg"
 472       },
 473       {
 474         "netclass": "Power",
 475         "pattern": "/USB_5V_Dbg"
 476       },
 477       {
 478         "netclass": "Power",
 479         "pattern": "/USB_DM_Dbg"
 480       },
 481       {
 482         "netclass": "Power",
 483         "pattern": "/USB_DP_Dbg"
 484       },
 485       {
 486         "netclass": "Power",
 487         "pattern": "DGND"
 488       },
 489       {
 490         "netclass": "Power",
 491         "pattern": "USB_DM2"
 492       },
 493       {
 494         "netclass": "Power",
 495         "pattern": "USB_DM3"
 496       },
 497       {
 498         "netclass": "Power",
 499         "pattern": "USB_DP2"
 500       },
 501       {
 502         "netclass": "Power",
 503         "pattern": "USB_DP3"
 504       }
 505     ]
 506   },
 507   "pcbnew": {
 508     "last_paths": {
 509       "gencad": "",
 510       "idf": "",
 511       "netlist": "OPiZero2_Rack.net",
 512       "specctra_dsn": "",
 513       "step": "",
 514       "vrml": ""
 515     },
 516     "page_layout_descr_file": "${KICAD7_TEMPLATE_DIR}/pagelayout.kicad_wks"
 517   },
 518   "schematic": {
 519     "annotate_start_num": 0,
 520     "drawing": {
 521       "dashed_lines_dash_length_ratio": 12.0,
 522       "dashed_lines_gap_length_ratio": 3.0,
 523       "default_line_thickness": 6.0,
 524       "default_text_size": 60.0,
 525       "field_names": [],
 526       "intersheets_ref_own_page": false,
 527       "intersheets_ref_prefix": "",
 528       "intersheets_ref_short": false,
 529       "intersheets_ref_show": false,
 530       "intersheets_ref_suffix": "",
 531       "junction_size_choice": 3,
 532       "label_size_ratio": 0.25,
 533       "pin_symbol_size": 0.0,
 534       "text_offset_ratio": 0.08
 535     },
 536     "legacy_lib_dir": "",
 537     "legacy_lib_list": [],
 538     "meta": {
 539       "version": 1
 540     },
 541     "net_format_name": "Pcbnew",
 542     "ngspice": {
 543       "fix_include_paths": true,
 544       "fix_passive_vals": false,
 545       "meta": {
 546         "version": 0
 547       },
 548       "model_mode": 0,
 549       "workbook_filename": ""
 550     },
 551     "page_layout_descr_file": "../../../Lib/pagelayout.kicad_wks",
 552     "plot_directory": "",
 553     "spice_adjust_passive_values": false,
 554     "spice_current_sheet_as_root": false,
 555     "spice_external_command": "spice \"%I\"",
 556     "spice_model_current_sheet_as_root": true,
 557     "spice_save_all_currents": false,
 558     "spice_save_all_voltages": false,
 559     "subpart_first_id": 65,
 560     "subpart_id_separator": 0
 561   },
 562   "sheets": [
 563     [
 564       "601c3a5c-2717-43a8-9e1a-1adbb2753cbd",
 565       ""
 566     ]
 567   ],
 568   "text_variables": {}
 569 }