git.techno-innov.fr Git - elec/adapters/orangepi/blob - OPiZero_Power_Exp/OPiZero_Power_Exp.kicad_pro

   1 {
   2   "board": {
   3     "design_settings": {
   4       "defaults": {
   5         "board_outline_line_width": 0.381,
   6         "copper_line_width": 0.381,
   7         "copper_text_italic": false,
   8         "copper_text_size_h": 1.524,
   9         "copper_text_size_v": 2.032,
  10         "copper_text_thickness": 0.30479999999999996,
  11         "copper_text_upright": false,
  12         "courtyard_line_width": 0.049999999999999996,
  13         "dimension_precision": 4,
  14         "dimension_units": 3,
  15         "dimensions": {
  16           "arrow_length": 1270000,
  17           "extension_offset": 500000,
  18           "keep_text_aligned": true,
  19           "suppress_zeroes": false,
  20           "text_position": 0,
  21           "units_format": 1
  22         },
  23         "fab_line_width": 0.09999999999999999,
  24         "fab_text_italic": false,
  25         "fab_text_size_h": 1.0,
  26         "fab_text_size_v": 1.0,
  27         "fab_text_thickness": 0.15,
  28         "fab_text_upright": false,
  29         "other_line_width": 0.09999999999999999,
  30         "other_text_italic": false,
  31         "other_text_size_h": 1.0,
  32         "other_text_size_v": 1.0,
  33         "other_text_thickness": 0.15,
  34         "other_text_upright": false,
  35         "pads": {
  36           "drill": 2.5,
  37           "height": 2.5,
  38           "width": 2.5
  39         },
  40         "silk_line_width": 0.22097999999999998,
  41         "silk_text_italic": false,
  42         "silk_text_size_h": 1.524,
  43         "silk_text_size_v": 1.524,
  44         "silk_text_thickness": 0.30479999999999996,
  45         "silk_text_upright": false,
  46         "zones": {
  47           "45_degree_only": false,
  48           "min_clearance": 0.15
  49         }
  50       },
  51       "diff_pair_dimensions": [
  52         {
  53           "gap": 0.0,
  54           "via_gap": 0.0,
  55           "width": 0.0
  56         }
  57       ],
  58       "drc_exclusions": [],
  59       "meta": {
  60         "filename": "board_design_settings.json",
  61         "version": 2
  62       },
  63       "rule_severities": {
  64         "annular_width": "error",
  65         "clearance": "error",
  66         "copper_edge_clearance": "error",
  67         "courtyards_overlap": "error",
  68         "diff_pair_gap_out_of_range": "error",
  69         "diff_pair_uncoupled_length_too_long": "error",
  70         "drill_out_of_range": "error",
  71         "duplicate_footprints": "warning",
  72         "extra_footprint": "warning",
  73         "footprint_type_mismatch": "error",
  74         "hole_clearance": "error",
  75         "hole_near_hole": "error",
  76         "invalid_outline": "error",
  77         "item_on_disabled_layer": "error",
  78         "items_not_allowed": "error",
  79         "length_out_of_range": "error",
  80         "malformed_courtyard": "error",
  81         "microvia_drill_out_of_range": "error",
  82         "missing_courtyard": "ignore",
  83         "missing_footprint": "warning",
  84         "net_conflict": "warning",
  85         "npth_inside_courtyard": "ignore",
  86         "padstack": "error",
  87         "pth_inside_courtyard": "ignore",
  88         "shorting_items": "error",
  89         "silk_over_copper": "warning",
  90         "silk_overlap": "warning",
  91         "skew_out_of_range": "error",
  92         "through_hole_pad_without_hole": "error",
  93         "too_many_vias": "error",
  94         "track_dangling": "warning",
  95         "track_width": "error",
  96         "tracks_crossing": "error",
  97         "unconnected_items": "error",
  98         "unresolved_variable": "error",
  99         "via_dangling": "warning",
 100         "zone_has_empty_net": "error",
 101         "zones_intersect": "error"
 102       },
 103       "rule_severitieslegacy_courtyards_overlap": true,
 104       "rule_severitieslegacy_no_courtyard_defined": false,
 105       "rules": {
 106         "allow_blind_buried_vias": false,
 107         "allow_microvias": false,
 108         "max_error": 0.005,
 109         "min_clearance": 0.0,
 110         "min_copper_edge_clearance": 0.1905,
 111         "min_hole_clearance": 0.25,
 112         "min_hole_to_hole": 0.25,
 113         "min_microvia_diameter": 0.508,
 114         "min_microvia_drill": 0.127,
 115         "min_silk_clearance": 0.0,
 116         "min_through_hole_diameter": 0.3,
 117         "min_track_width": 0.2032,
 118         "min_via_annular_width": 0.049999999999999996,
 119         "min_via_diameter": 0.508,
 120         "use_height_for_length_calcs": true
 121       },
 122       "track_widths": [
 123         0.0
 124       ],
 125       "via_dimensions": [
 126         {
 127           "diameter": 0.0,
 128           "drill": 0.0
 129         }
 130       ],
 131       "zones_allow_external_fillets": false,
 132       "zones_use_no_outline": true
 133     },
 134     "layer_presets": []
 135   },
 136   "boards": [],
 137   "cvpcb": {
 138     "equivalence_files": []
 139   },
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 314     ],
 315     "rule_severities": {
 316       "bus_definition_conflict": "error",
 317       "bus_entry_needed": "error",
 318       "bus_label_syntax": "error",
 319       "bus_to_bus_conflict": "error",
 320       "bus_to_net_conflict": "error",
 321       "different_unit_footprint": "error",
 322       "different_unit_net": "error",
 323       "duplicate_reference": "error",
 324       "duplicate_sheet_names": "error",
 325       "extra_units": "error",
 326       "global_label_dangling": "warning",
 327       "hier_label_mismatch": "error",
 328       "label_dangling": "error",
 329       "lib_symbol_issues": "warning",
 330       "multiple_net_names": "warning",
 331       "net_not_bus_member": "warning",
 332       "no_connect_connected": "warning",
 333       "no_connect_dangling": "warning",
 334       "pin_not_connected": "error",
 335       "pin_not_driven": "error",
 336       "pin_to_pin": "warning",
 337       "power_pin_not_driven": "error",
 338       "similar_labels": "warning",
 339       "unannotated": "error",
 340       "unit_value_mismatch": "error",
 341       "unresolved_variable": "error",
 342       "wire_dangling": "error"
 343     }
 344   },
 345   "libraries": {
 346     "pinned_footprint_libs": [],
 347     "pinned_symbol_libs": []
 348   },
 349   "meta": {
 350     "filename": "OPiZero_Power_Exp.kicad_pro",
 351     "version": 1
 352   },
 353   "net_settings": {
 354     "classes": [
 355       {
 356         "bus_width": 12.0,
 357         "clearance": 0.185,
 358         "diff_pair_gap": 0.25,
 359         "diff_pair_via_gap": 0.25,
 360         "diff_pair_width": 0.25,
 361         "line_style": 0,
 362         "microvia_diameter": 0.508,
 363         "microvia_drill": 0.127,
 364         "name": "Default",
 365         "pcb_color": "rgba(0, 0, 0, 0.000)",
 366         "schematic_color": "rgba(0, 0, 0, 0.000)",
 367         "track_width": 0.2032,
 368         "via_diameter": 0.508,
 369         "via_drill": 0.3,
 370         "wire_width": 6.0
 371       },
 372       {
 373         "bus_width": 12.0,
 374         "clearance": 0.19304,
 375         "diff_pair_gap": 0.25,
 376         "diff_pair_via_gap": 0.25,
 377         "diff_pair_width": 0.25,
 378         "line_style": 0,
 379         "microvia_diameter": 0.508,
 380         "microvia_drill": 0.127,
 381         "name": "HighPower",
 382         "nets": [],
 383         "pcb_color": "rgba(0, 0, 0, 0.000)",
 384         "schematic_color": "rgba(0, 0, 0, 0.000)",
 385         "track_width": 0.508,
 386         "via_diameter": 1.0,
 387         "via_drill": 0.5,
 388         "wire_width": 6.0
 389       },
 390       {
 391         "bus_width": 12.0,
 392         "clearance": 0.19304,
 393         "diff_pair_gap": 0.25,
 394         "diff_pair_via_gap": 0.25,
 395         "diff_pair_width": 0.25,
 396         "line_style": 0,
 397         "microvia_diameter": 0.508,
 398         "microvia_drill": 0.127,
 399         "name": "Power",
 400         "nets": [
 401           "+3.3V",
 402           "+5C",
 403           "+VCC",
 404           "/5VDebug",
 405           "/5VInd",
 406           "/CMD_FAN",
 407           "/CMD_FAN_Filt",
 408           "/Ch1",
 409           "/Ch2",
 410           "/Ch3",
 411           "/USBVio_Dbg",
 412           "/USB_5VFilt_Dbg",
 413           "/USB_5V_Dbg",
 414           "/USB_DM_Dbg",
 415           "/USB_DP_Dbg",
 416           "DGND",
 417           "USB_DM2",
 418           "USB_DM3",
 419           "USB_DP2",
 420           "USB_DP3"
 421         ],
 422         "pcb_color": "rgba(0, 0, 0, 0.000)",
 423         "schematic_color": "rgba(0, 0, 0, 0.000)",
 424         "track_width": 0.3,
 425         "via_diameter": 0.508,
 426         "via_drill": 0.3,
 427         "wire_width": 6.0
 428       }
 429     ],
 430     "meta": {
 431       "version": 2
 432     },
 433     "net_colors": null
 434   },
 435   "pcbnew": {
 436     "last_paths": {
 437       "gencad": "",
 438       "idf": "",
 439       "netlist": "OPiZero_Power_Exp.net",
 440       "specctra_dsn": "",
 441       "step": "",
 442       "vrml": ""
 443     },
 444     "page_layout_descr_file": "${KICAD7_TEMPLATE_DIR}/pagelayout.kicad_wks"
 445   },
 446   "schematic": {
 447     "annotate_start_num": 0,
 448     "drawing": {
 449       "default_line_thickness": 6.0,
 450       "default_text_size": 60.0,
 451       "field_names": [],
 452       "intersheets_ref_own_page": false,
 453       "intersheets_ref_prefix": "",
 454       "intersheets_ref_short": false,
 455       "intersheets_ref_show": false,
 456       "intersheets_ref_suffix": "",
 457       "junction_size_choice": 3,
 458       "label_size_ratio": 0.25,
 459       "pin_symbol_size": 0.0,
 460       "text_offset_ratio": 0.08
 461     },
 462     "legacy_lib_dir": "",
 463     "legacy_lib_list": [],
 464     "meta": {
 465       "version": 1
 466     },
 467     "net_format_name": "Pcbnew",
 468     "ngspice": {
 469       "fix_include_paths": true,
 470       "fix_passive_vals": false,
 471       "meta": {
 472         "version": 0
 473       },
 474       "model_mode": 0,
 475       "workbook_filename": ""
 476     },
 477     "page_layout_descr_file": "../../../Lib/pagelayout.kicad_wks",
 478     "plot_directory": "",
 479     "spice_adjust_passive_values": false,
 480     "spice_external_command": "spice \"%I\"",
 481     "subpart_first_id": 65,
 482     "subpart_id_separator": 0
 483   },
 484   "sheets": [
 485     [
 486       "601c3a5c-2717-43a8-9e1a-1adbb2753cbd",
 487       ""
 488     ]
 489   ],
 490   "text_variables": {}
 491 }