First fixes to OPiZero2_Rack board

[elec/adapters/orangepi] / OPiZero2_Rack / OPiZero2_Rack.kicad_pro

diff --git a/OPiZero2_Rack/OPiZero2_Rack.kicad_pro b/OPiZero2_Rack/OPiZero2_Rack.kicad_pro
index c1fc967..c05a02b 100644 (file)
--- a/OPiZero2_Rack/OPiZero2_Rack.kicad_pro
+++ b/OPiZero2_Rack/OPiZero2_Rack.kicad_pro
@@ -1,5 +1,6 @@
 {
   "board": {
+    "3dviewports": [],
     "design_settings": {
       "defaults": {
         "board_outline_line_width": 0.381,
@@ -131,7 +132,8 @@
       "zones_allow_external_fillets": false,
       "zones_use_no_outline": true
     },
-    "layer_presets": []
+    "layer_presets": [],
+    "viewports": []
   },
   "boards": [],
   "cvpcb": {
@@ -315,18 +317,23 @@
     "rule_severities": {
       "bus_definition_conflict": "error",
       "bus_entry_needed": "error",
-      "bus_label_syntax": "error",
       "bus_to_bus_conflict": "error",
       "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
       "different_unit_footprint": "error",
       "different_unit_net": "error",
       "duplicate_reference": "error",
       "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
       "extra_units": "error",
       "global_label_dangling": "warning",
       "hier_label_mismatch": "error",
       "label_dangling": "error",
       "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
       "multiple_net_names": "warning",
       "net_not_bus_member": "warning",
       "no_connect_connected": "warning",
@@ -336,6 +343,7 @@
       "pin_to_pin": "warning",
       "power_pin_not_driven": "error",
       "similar_labels": "warning",
+      "simulation_model_issue": "ignore",
       "unannotated": "error",
       "unit_value_mismatch": "error",
       "unresolved_variable": "error",
@@ -353,7 +361,7 @@
   "net_settings": {
     "classes": [
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.185,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -367,10 +375,10 @@
         "track_width": 0.2032,
         "via_diameter": 0.508,
         "via_drill": 0.3,
-        "wire_width": 6.0
+        "wire_width": 6
       },
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.19304,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -379,16 +387,15 @@
         "microvia_diameter": 0.508,
         "microvia_drill": 0.127,
         "name": "HighPower",
-        "nets": [],
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "schematic_color": "rgba(0, 0, 0, 0.000)",
         "track_width": 0.508,
         "via_diameter": 1.0,
         "via_drill": 0.5,
-        "wire_width": 6.0
+        "wire_width": 6
       },
       {
-        "bus_width": 12.0,
+        "bus_width": 12,
         "clearance": 0.19304,
         "diff_pair_gap": 0.25,
         "diff_pair_via_gap": 0.25,
@@ -397,41 +404,105 @@
         "microvia_diameter": 0.508,
         "microvia_drill": 0.127,
         "name": "Power",
-        "nets": [
-          "+3.3V",
-          "+5C",
-          "+VCC",
-          "+VCC3",
-          "/5VDebug",
-          "/5VInd",
-          "/CMD_FAN",
-          "/CMD_FAN_Filt",
-          "/Ch1",
-          "/Ch2",
-          "/Ch3",
-          "/USBVio_Dbg",
-          "/USB_5VFilt_Dbg",
-          "/USB_5V_Dbg",
-          "/USB_DM_Dbg",
-          "/USB_DP_Dbg",
-          "DGND",
-          "USB_DM2",
-          "USB_DM3",
-          "USB_DP2",
-          "USB_DP3"
-        ],
         "pcb_color": "rgba(0, 0, 0, 0.000)",
         "schematic_color": "rgba(0, 0, 0, 0.000)",
         "track_width": 0.3,
         "via_diameter": 0.508,
         "via_drill": 0.3,
-        "wire_width": 6.0
+        "wire_width": 6
       }
     ],
     "meta": {
-      "version": 2
+      "version": 3
     },
-    "net_colors": null
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": [
+      {
+        "netclass": "Power",
+        "pattern": "+3.3V"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "+5C"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "+VCC"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "+VCC3"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/5VDebug"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/5VInd"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/CMD_FAN"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/CMD_FAN_Filt"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/Ch1"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/Ch2"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/Ch3"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/USBVio_Dbg"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/USB_5VFilt_Dbg"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/USB_5V_Dbg"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/USB_DM_Dbg"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "/USB_DP_Dbg"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "DGND"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "USB_DM2"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "USB_DM3"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "USB_DP2"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "USB_DP3"
+      }
+    ]
   },
   "pcbnew": {
     "last_paths": {
@@ -442,11 +513,13 @@
       "step": "",
       "vrml": ""
     },
-    "page_layout_descr_file": "${KICAD6_FOOTPRINT_DIR}/pagelayout.kicad_wks"
+    "page_layout_descr_file": "${KICAD7_TEMPLATE_DIR}/pagelayout.kicad_wks"
   },
   "schematic": {
     "annotate_start_num": 0,
     "drawing": {
+      "dashed_lines_dash_length_ratio": 12.0,
+      "dashed_lines_gap_length_ratio": 3.0,
       "default_line_thickness": 6.0,
       "default_text_size": 60.0,
       "field_names": [],
@@ -478,7 +551,11 @@
     "page_layout_descr_file": "../../../Lib/pagelayout.kicad_wks",
     "plot_directory": "",
     "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
     "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
     "subpart_first_id": 65,
     "subpart_id_separator": 0
   },