Add support for GPIO filtering clock divider configuration.

diff --git a/core/system.c b/core/system.c
index ef38561..d9898ee 100644 (file)
--- a/core/system.c
+++ b/core/system.c
@@ -445,6 +445,35 @@ static void propagate_main_clock(void)
 }
 
 
+/***************************************************************************** */
+/*                    GPIO Filtering CLK dividers                              */
+/***************************************************************************** */
+/* Configure a GPIO filtering clock divider
+ * There are 7 clock dividers which can be used by any GPIO to filter input glitches
+ * Filter clock selection is made per GPIO among one of the seven available filter clocks
+ * wich are derived from the main clock and divided by a value configured in the
+ * IO_config_clk_div[] registers.
+ * clk_div is a value between 0 and 255, with 0 disabling the divider.
+ */
+
+void config_gpio_filtering_clk_divider(uint8_t clk_num, uint8_t clk_div)
+{
+       struct lpc_sys_config* sys_config = LPC_SYS_CONFIG;
+
+       if (clk_num > 6) {
+               return;
+       }
+       sys_config->IO_config_clk_div[6 - clk_num] = clk_div;
+}
+uint8_t get_gpio_filtering_clk_divider(uint8_t clk_num)
+{
+       struct lpc_sys_config* sys_config = LPC_SYS_CONFIG;
+       if (clk_num > 6) {
+               return 0;
+       }
+       return sys_config->IO_config_clk_div[clk_num];
+}
+
 /***************************************************************************** */
 /*                    CLK Out                                                  */
 /***************************************************************************** */

diff --git a/include/core/system.h b/include/core/system.h
index df886e9..c3189f0 100644 (file)
--- a/include/core/system.h
+++ b/include/core/system.h
@@ -147,6 +147,25 @@ void clock_config(uint32_t freq_sel);
 uint32_t get_main_clock(void);
 
 
+/***************************************************************************** */
+/*                    GPIO Filtering CLK dividers                              */
+/***************************************************************************** */
+/* Configure a GPIO filtering clock divider
+ * There are 7 clock dividers which can be used by any GPIO to filter input glitches
+ * Filter clock selection is made per GPIO among one of the seven available filter clocks
+ * wich are derived from the main clock and divided by a value configured in the
+ * IO_config_clk_div[] registers.
+ * clk_div is a value between 0 and 255, with 0 disabling the divider.
+ */
+
+void config_gpio_filtering_clk_divider(uint8_t clk_num, uint8_t clk_div);
+uint8_t get_gpio_filtering_clk_divider(uint8_t clk_num);
+
+
+/***************************************************************************** */
+/*                    CLK Out                                                  */
+/***************************************************************************** */
+
 /* This is mainly a debug feature, but can be used to provide a clock to an
  * external peripheral */
 void clkout_on(uint32_t src, uint32_t div);