Fix comments

diff --git a/include/core/lpc_core.h b/include/core/lpc_core.h
index d2f4658..8d4a895 100644 (file)
--- a/include/core/lpc_core.h
+++ b/include/core/lpc_core.h
@@ -295,17 +295,17 @@ static inline void lpc_disable_irq(void)
 
 /* Cortex-M0 NVIC Registers */
 struct nvic_regs {
-       volatile uint32_t int_set_enable;  /* 0x000 : Interrupt Set Enable Register (R/W) */
+       volatile uint32_t int_set_enable;  /* 0x000 : ISER : Interrupt Set Enable Register (R/W) */
        uint32_t reserved_0[31];
-       volatile uint32_t int_clear_enable;  /* 0x080 : Interrupt Clear Enable Register (R/W) */
+       volatile uint32_t int_clear_enable;  /* 0x080 : ICER : Interrupt Clear Enable Register (R/W) */
        uint32_t reserved_1[31];
-       volatile uint32_t int_set_pending;  /* 0x100 : Interrupt Set Pending Register (R/W) */
+       volatile uint32_t int_set_pending;  /* 0x100 : ISPR : Interrupt Set Pending Register (R/W) */
        uint32_t reserved_2[31];
-       volatile uint32_t int_clear_pending;  /* 0x180 : Interrupt Clear Pending Register (R/W) */
+       volatile uint32_t int_clear_pending;  /* 0x180 : ICPR Interrupt Clear Pending Register (R/W) */
        uint32_t reserved_3[31];
-       volatile uint32_t int_active_bit; /* 0x200 : Interrupt Active Bit Register (R/-) */
+       volatile uint32_t int_active_bit; /* 0x200 : IABR : Interrupt Active Bit Register (R/-) */
        uint32_t reserved_4[63];
-       volatile uint32_t int_priority[8]; /* 0x3EC : Interrupt Priority Register (R/W) */
+       volatile uint32_t int_priority[8]; /* 0x300 : Interrupt Priority Register (R/W) */
 };
 #define LPC_NVIC      ((struct nvic_regs *) LPC_NVIC_BASE)        /* NVIC configuration struct */