return ret;
}
+int cc1101_handle_rx_err(uint8_t* status)
+{
+ uint8_t st_buff[2];
+ uint8_t rx_status = 0, pkt_status = 0;
+
+ /* Check that we are in an error state */
+ rx_status = cc1101_read_reg(CC1101_STATUS(rx_bytes));
+ if (rx_status != 0) {
+ return -CC1101_ERR_NO_RX_ERR;
+ }
+ pkt_status = cc1101_read_reg(CC1101_STATUS(packet_status));
+ if (status != NULL) {
+ *status = pkt_status;
+ }
+ cc1101_read_burst_reg(CC1101_FIFO_BURST, st_buff, 2);
+ cc1101.link_quality = st_buff[1];
+ cc1101.rx_sig_strength = st_buff[0];
+
+ rx_status = cc1101_read_reg(CC1101_STATUS(rx_bytes));
+ if (rx_status == 0) {
+ cc1101_flush_rx_fifo();
+ }
+ /* CRC error */
+ if (!(cc1101.link_quality & CC1101_CRC_OK)) {
+ cc1101_flush_rx_fifo();
+ return -CC1101_ERR_CRC;
+ }
+ /* Overflow ? */
+ if (rx_status & CC1101_RX_FIFO_OVERFLOW) {
+ cc1101_flush_rx_fifo();
+ return -CC1101_ERR_OVERFLOW;
+ }
+ return rx_status;
+}
+
+
/***************************************************************************** */
/* CC1101 Initialisation */
#define CC1101_ERR_INCOMPLET_PACKET (CC1101_ERR_BASE + 3)
#define CC1101_ERR_OVERFLOW (CC1101_ERR_BASE + 4)
#define CC1101_ERR_CRC (CC1101_ERR_BASE + 5)
+#define CC1101_ERR_NO_RX_ERR (CC1101_ERR_BASE + 6)
/* Definitions for chip status */
int cc1101_receive_packet(uint8_t* buffer, uint8_t size, uint8_t* status);
+int cc1101_handle_rx_err(uint8_t* status);
/***************************************************************************** */
/* CC1101 Initialisation */
void cc1101_set_address(uint8_t address);
/* Set current channel to use.
- * The caller is responsible for checking that the channel spacing and channel bandwith are configures
+ * The caller is responsible for checking that the channel spacing and channel bandwith are configured
* correctly to prevent overlaping channels, or to use only non-overlaping channel numbers.
* This function places the CC1101 chip in idle state.
*/