From: Nathael Pajani <nathael.pajani@ed3l.fr>
Date: Wed, 13 Sep 2017 08:52:46 +0000 (+0200)
Subject: Scialys uC : Adding SDA and SCL labels
X-Git-Url: http://git.techno-innov.fr/?a=commitdiff_plain;h=33c475766abaf52cfa156ca049c3cc71188d909b;p=elec%2Fboards%2Fscialys

Scialys uC : Adding SDA and SCL labels
---

diff --git a/Scialys_uC/Scialys_uC.kicad_pcb b/Scialys_uC/Scialys_uC.kicad_pcb
index e748532..442bc75 100644
--- a/Scialys_uC/Scialys_uC.kicad_pcb
+++ b/Scialys_uC/Scialys_uC.kicad_pcb
@@ -3,9 +3,9 @@
   (general
     (links 133)
     (no_connects 0)
-    (area 157.309499 63.309499 193.790501 123.190501)
+    (area 131.39964 57.9488 203.829602 139.999721)
     (thickness 1.6002)
-    (drawings 74)
+    (drawings 76)
     (tracks 891)
     (zones 0)
     (modules 44)
@@ -1740,6 +1740,12 @@
     )
   )
 
+  (gr_text SCL (at 164.8 101.05) (layer B.SilkS)
+    (effects (font (size 0.8 0.8) (thickness 0.15)) (justify mirror))
+  )
+  (gr_text SDA (at 164.9 99.05) (layer B.SilkS)
+    (effects (font (size 0.8 0.8) (thickness 0.15)) (justify mirror))
+  )
   (gr_text "Techno-Innov\nScialys - v0.5\nµC Board\nCC-by-sa-nc" (at 166.85 111 270) (layer F.SilkS)
     (effects (font (size 0.8 0.8) (thickness 0.15)))
   )