From: Nathael Pajani <nathael.pajani@ed3l.fr>
Date: Wed, 26 Aug 2015 21:13:17 +0000 (+0200)
Subject: Oups ! That's better with the parenthesis ... There's still so much to be tested ...
X-Git-Url: http://git.techno-innov.fr/?a=commitdiff_plain;h=a302d2f8cfaaf43a696090b8548af93ef77bac95;p=soft%2Flpc122x%2Fcore

Oups ! That's better with the parenthesis ... There's still so much to be tested ...
---

diff --git a/include/core/lpc_core_cm0.h b/include/core/lpc_core_cm0.h
index 657d509..6e340b5 100644
--- a/include/core/lpc_core_cm0.h
+++ b/include/core/lpc_core_cm0.h
@@ -57,11 +57,11 @@ static inline uint32_t get_APSR(void)
 {
 	uint32_t r; __asm volatile ("mrs %0, apsr" : "=r" (r)); return (r);
 }
-#define APSR_SATURATION  (get_APSR & (0x1 << 27))  /* bit 27  Saturation condition flag */
-#define APSR_OVERFLOW    (get_APSR & (0x1 << 28))  /* bit 28  Overflow condition code flag */
-#define APSR_CARRY       (get_APSR & (0x1 << 29))  /* bit 29  Carry condition code flag */
-#define APSR_ZERO        (get_APSR & (0x1 << 30))  /* bit 30  Zero condition code flag */
-#define APSR_NEGATIVE    (get_APSR & (0x1 << 31))  /* bit 31  Negative condition code flag */
+#define APSR_SATURATION  (get_APSR() & (0x1 << 27))  /* bit 27  Saturation condition flag */
+#define APSR_OVERFLOW    (get_APSR() & (0x1 << 28))  /* bit 28  Overflow condition code flag */
+#define APSR_CARRY       (get_APSR() & (0x1 << 29))  /* bit 29  Carry condition code flag */
+#define APSR_ZERO        (get_APSR() & (0x1 << 30))  /* bit 30  Zero condition code flag */
+#define APSR_NEGATIVE    (get_APSR() & (0x1 << 31))  /* bit 31  Negative condition code flag */
 
 
 /* Access the Interrupt Program Status Register (IPSR). */
@@ -69,7 +69,7 @@ static inline uint32_t get_IPSR(void)
 {
 	uint32_t r; __asm volatile ("mrs %0, ipsr" : "=r" (r)); return (r);
 }
-#define IPSR      (get_IPSR & 0x1FF)  /* bit:  0..8  Exception number */
+#define IPSR      (get_IPSR() & 0x1FF)  /* bit:  0..8  Exception number */
 #define IPSR_IRQ0 16
 #define IRQ_NUM   (IPSR - IPSR_IRQ0)