3 TARGET_DIR = apps/$(MODULE)/$(NAME)
9 CROSS_COMPILE ?= arm-none-eabi-
10 CC = $(CROSS_COMPILE)gcc
11 FOPTS = -fno-builtin -ffunction-sections -fdata-sections -ffreestanding
12 CFLAGS = -Wall -g -O2 -mthumb -mcpu=$(CPU) $(FOPTS)
13 LINKOPTS = -static -g -nostartfiles -nostdlib \
14 -Wl,--gc-sections -Wl,--build-id=none \
15 -Wl,-Map=$(TARGET_DIR)/lpc_map_$(LPC).map -Tlpc_link_$(LPC).ld
18 APPS = $(subst apps/,,$(wildcard apps/*/*))
24 TARGET_INCLUDES = $(TARGET_DIR)/
27 SRC = $(wildcard */*.c)
28 SRC += $(wildcard lib/*/*.c)
29 SRC += $(wildcard lib/protocols/*/*.c)
30 OBJS = ${SRC:%.c=${OBJDIR}/%.o}
31 DEPS = ${OBJS:%.o=$(OBJDIR)/%.d}
33 NAME_SRC = $(wildcard $(TARGET_DIR)/*.c)
34 NAME_OBJS = ${NAME_SRC:%.c=${OBJDIR}/%.o}
35 NAME_DEPS = ${NAME_OBJS:%.o=$(OBJDIR)/%.d}
37 -include $(DEPS) $(NAME_DEPS)
39 .SECONDARY: $(OBJS) $(NAME_OBJS)
41 %.elf: $(OBJS) $(NAME_OBJS)
42 @echo "Linking $(MODULE)/$(NAME) ..."
43 @$(CC) $(LINKOPTS) $(OBJS) $(NAME_OBJS) -o $@
46 @echo "Creating image :
\e[32m$@
\e[39m"
47 @$(CROSS_COMPILE)objcopy -R .stack -R .bss -O binary $^ $@
49 @$(CROSS_COMPILE)size $^
54 @echo "-- compiling" $<
55 @$(CC) -MMD -MP -MF ${OBJDIR}/$*.d $(CFLAGS) $< -c -o $@ -I$(INCLUDES) -I$(TARGET_INCLUDES)
59 @make --no-print-directory MODULE=$(shell dirname $@) NAME=$(shell basename $@) apps/$(shell dirname $@)/$(shell basename $@)/$(shell basename $@).bin
67 rm -f apps/*/*/*.bin apps/*/*/*.elf apps/*/*/*.map
71 # The command "make -f /path/to/here/Makefile module/app_name" does not work, as well
72 # as the command "make -f /path/to/here/apps/module/app_name/Makefile".
73 # This could be solved in the app Makefiles by replacing
74 # "NAME = $(shell basename $(CURDIR))"
76 # "NAME = $(shell basename $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST)))))"
77 # and possibly some similar trick for the base Makefile but this is just
78 # unreadable and moslty unusefull, so it won't be supported.
79 # Use "make -C /path/to/here/ module/app_name" or "make -C /path/to/here/apps/module/app_name"