Typo fix in defines names for AHB (and not ABH)
authorNathael Pajani <nathael.pajani@ed3l.fr>
Mon, 19 Apr 2021 22:31:29 +0000 (00:31 +0200)
committerNathael Pajani <nathael.pajani@ed3l.fr>
Mon, 19 Apr 2021 22:31:29 +0000 (00:31 +0200)
core/pio.c
core/system.c
core/watchdog.c
drivers/adc.c
drivers/gpio.c
drivers/i2c.c
drivers/sctimers.c
drivers/serial.c
include/core/system.h

index 77b8ee8..909a473 100644 (file)
@@ -71,13 +71,13 @@ static volatile uint32_t* pio_regs_handles_port0[PORT0_NB_PINS] = {
 /* To change GPIO config the io config block must be powered on */
 static void io_config_clk_on(void)
 {
-    subsystem_power(LPC_SYS_ABH_CLK_CTRL_IO_CONFIG, 1);
-    subsystem_power(LPC_SYS_ABH_CLK_CTRL_SWM, 1);
+    subsystem_power(LPC_SYS_AHB_CLK_CTRL_IO_CONFIG, 1);
+    subsystem_power(LPC_SYS_AHB_CLK_CTRL_SWM, 1);
 }
 static void io_config_clk_off(void)
 {
-    subsystem_power(LPC_SYS_ABH_CLK_CTRL_IO_CONFIG, 0);
-    subsystem_power(LPC_SYS_ABH_CLK_CTRL_SWM, 0);
+    subsystem_power(LPC_SYS_AHB_CLK_CTRL_IO_CONFIG, 0);
+    subsystem_power(LPC_SYS_AHB_CLK_CTRL_SWM, 0);
 }
 
 
index c52e09e..c0a2dbf 100644 (file)
@@ -83,7 +83,7 @@ void system_set_default_power_state(void)
 {
        struct lpc_sys_config* sys_config = LPC_SYS_CONFIG;
        /* Start with all memory powered on and nothing else */
-       sys_config->sys_AHB_clk_ctrl = LPC_SYS_ABH_CLK_CTRL_MEM_ALL;
+       sys_config->sys_AHB_clk_ctrl = LPC_SYS_AHB_CLK_CTRL_MEM_ALL;
 }
 
 /* Enter deep sleep.
index 5553fa8..96445d8 100644 (file)
@@ -112,7 +112,7 @@ void watchdog_config(const struct wdt_config* wd_conf)
 
        NVIC_DisableIRQ(WDT_IRQ);
        /* Power wadchdog block before changing it's configuration */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_Watchdog, 1);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_Watchdog, 1);
        /* Configure watchdog timeout for normal operation */
        wdt->timer_const = ((wd_conf->nb_clk >> 2) & LPC_WDT_TIMER_MAX);
        /* If intr_mode_only is set, a watchdog timeout will trigger an interrupt instead of a reset */
@@ -174,9 +174,9 @@ int stop_watchdog(void)
                return -1;
        }
        NVIC_DisableIRQ(WDT_IRQ);
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_Watchdog, 1);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_Watchdog, 1);
        sys_config->powerdown_run_cfg |= LPC_POWER_DOWN_WDT_OSC;
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_Watchdog, 0);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_Watchdog, 0);
        return 0;
 }
 
@@ -192,12 +192,12 @@ void startup_watchdog_disable(void)
        struct lpc_watchdog* wdt = LPC_WDT;
 
        /* Power wadchdog block before changing it's configuration */
-       sys_config->sys_AHB_clk_ctrl |= LPC_SYS_ABH_CLK_CTRL_Watchdog;
+       sys_config->sys_AHB_clk_ctrl |= LPC_SYS_AHB_CLK_CTRL_Watchdog;
        /* Stop watchdog */
        wdt->mode = 0;
        watchdog_feed();
        /* And power it down */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_Watchdog, 0);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_Watchdog, 0);
        sys_config->powerdown_run_cfg |= LPC_POWER_DOWN_WDT_OSC;
        NVIC_DisableIRQ(WDT_IRQ);
 }
index ae9cdb4..85b1a71 100644 (file)
@@ -255,7 +255,7 @@ void adc_on(void (*adc_callback)(uint32_t))
        /* Power-up ADC */
        sys_config->powerdown_run_cfg &= ~LPC_POWER_DOWN_ADC;
        /* Provide clock to ADC */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_ADC, 1);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_ADC, 1);
        adc->ctrl = 0;
        adc_clk_update();
 
@@ -289,6 +289,6 @@ void adc_off(void)
        /* Power Down ADC */
        sys_config->powerdown_run_cfg |= LPC_POWER_DOWN_ADC;
        /* Remove clock from ADC block */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_ADC, 0);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_ADC, 0);
 }
 
index 8a95bd2..854fdc4 100644 (file)
 void gpio_on(void)
 {
        /* Provide power to GPIO control blocks */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_GPIO, 1);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_GPIO, 1);
 }
 void gpio_off(void)
 {
        /* Remove power from GPIO control blocks */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_GPIO, 0);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_GPIO, 0);
 }
 
 /*
@@ -100,7 +100,7 @@ int set_gpio_callback(void (*callback) (uint32_t), const struct pio* gpio, uint8
        }
 
        /* Power on the Pin interrupt subsystem */
-       subsystem_power(LPC_SYS_ABH_CLK_CTRL_GPIO, 1);
+       subsystem_power(LPC_SYS_AHB_CLK_CTRL_GPIO, 1);
 
        /* Configure the pin as interrupt source */
        gpio_port->data_dir &= ~(1 << gpio->pin); /* Input */
index 52ac0bd..fbe5e3e 100644 (file)
@@ -71,28 +71,28 @@ static struct i2c_bus i2c_buses[NB_I2C_BUSSES] = {
                .regs = (struct lpc_i2c*)LPC_I2C0,
                .irq = I2C0_IRQ,
                .reset_bit = LPC_I2C0_RESET_N,
-               .power_bit = LPC_SYS_ABH_CLK_CTRL_I2C0,
+               .power_bit = LPC_SYS_AHB_CLK_CTRL_I2C0,
                .state = I2C_OK,
        },
        {
                .regs = (struct lpc_i2c*)LPC_I2C1,
                .irq = I2C1_IRQ,
                .reset_bit = LPC_I2C1_RESET_N,
-               .power_bit = LPC_SYS_ABH_CLK_CTRL_I2C1,
+               .power_bit = LPC_SYS_AHB_CLK_CTRL_I2C1,
                .state = I2C_OK,
        },
        {
                .regs = (struct lpc_i2c*)LPC_I2C2,
                .irq = I2C2_IRQ,
                .reset_bit = LPC_I2C2_RESET_N,
-               .power_bit = LPC_SYS_ABH_CLK_CTRL_I2C2,
+               .power_bit = LPC_SYS_AHB_CLK_CTRL_I2C2,
                .state = I2C_OK,
        },
        {
                .regs = (struct lpc_i2c*)LPC_I2C3,
                .irq = I2C3_IRQ,
                .reset_bit = LPC_I2C3_RESET_N,
-               .power_bit = LPC_SYS_ABH_CLK_CTRL_I2C3,
+               .power_bit = LPC_SYS_AHB_CLK_CTRL_I2C3,
                .state = I2C_OK,
        },
 };
index 672f034..e3702c6 100644 (file)
@@ -55,7 +55,7 @@ struct sctimer_device
 
 struct sctimer_device sctimer = {
        .regs = LPC_SCTIMER,
-       .power_bit = LPC_SYS_ABH_CLK_CTRL_SCT,
+       .power_bit = LPC_SYS_AHB_CLK_CTRL_SCT,
        .reset = LPC_SCT_RESET_N,
        .irq = SCT_IRQ,
        .configured = 0,
index f74c789..1d175b2 100644 (file)
@@ -365,9 +365,9 @@ struct uart_def
        uint32_t power_offset;
 };
 static struct uart_def uart_defs[NUM_UARTS] = {
-       { UART0_IRQ, LPC_SYS_ABH_CLK_CTRL_UART0 },
-       { UART1_IRQ, LPC_SYS_ABH_CLK_CTRL_UART1 },
-       { UART2_IRQ, LPC_SYS_ABH_CLK_CTRL_UART2 },
+       { UART0_IRQ, LPC_SYS_AHB_CLK_CTRL_UART0 },
+       { UART1_IRQ, LPC_SYS_AHB_CLK_CTRL_UART1 },
+       { UART2_IRQ, LPC_SYS_AHB_CLK_CTRL_UART2 },
 };
 
 /***************************************************************************** */
index fe75606..e91ef27 100644 (file)
@@ -176,34 +176,34 @@ struct lpc_sys_config
 /* AHB control bits
  *   0 (System (cortexM0, syscon, PMU, ...)) is a read only bit (system cannot be disabled)
  */
-#define LPC_SYS_ABH_CLK_CTRL_SYSTEM     (1 <<  0) /* Read only */
-#define LPC_SYS_ABH_CLK_CTRL_ROM        (1 <<  1)
-#define LPC_SYS_ABH_CLK_CTRL_RAM        (1 <<  2)
-#define LPC_SYS_ABH_CLK_CTRL_FLASH_REG  (1 <<  3)
-#define LPC_SYS_ABH_CLK_CTRL_FLASH      (1 <<  4)
-#define LPC_SYS_ABH_CLK_CTRL_I2C0       (1 <<  5)
-#define LPC_SYS_ABH_CLK_CTRL_GPIO       (1 <<  6)
-#define LPC_SYS_ABH_CLK_CTRL_SWM        (1 <<  7)
-#define LPC_SYS_ABH_CLK_CTRL_SCT        (1 <<  8)
-#define LPC_SYS_ABH_CLK_CTRL_WKT        (1 <<  9)
-#define LPC_SYS_ABH_CLK_CTRL_MRT        (1 << 10)
-#define LPC_SYS_ABH_CLK_CTRL_SSP0       (1 << 11)
-#define LPC_SYS_ABH_CLK_CTRL_SSP1       (1 << 12)
-#define LPC_SYS_ABH_CLK_CTRL_CRC        (1 << 13)
-#define LPC_SYS_ABH_CLK_CTRL_UART0      (1 << 14)
-#define LPC_SYS_ABH_CLK_CTRL_UART1      (1 << 15)
-#define LPC_SYS_ABH_CLK_CTRL_UART2      (1 << 16)
-#define LPC_SYS_ABH_CLK_CTRL_Watchdog   (1 << 17)
-#define LPC_SYS_ABH_CLK_CTRL_IO_CONFIG  (1 << 18)
-#define LPC_SYS_ABH_CLK_CTRL_ACMP       (1 << 19)
-#define LPC_SYS_ABH_CLK_CTRL_I2C1       (1 << 21)
-#define LPC_SYS_ABH_CLK_CTRL_I2C2       (1 << 22)
-#define LPC_SYS_ABH_CLK_CTRL_I2C3       (1 << 23)
-#define LPC_SYS_ABH_CLK_CTRL_ADC        (1 << 24)
-#define LPC_SYS_ABH_CLK_CTRL_MTB        (1 << 26)
-#define LPC_SYS_ABH_CLK_CTRL_DMA        (1 << 29)
+#define LPC_SYS_AHB_CLK_CTRL_SYSTEM     (1 <<  0) /* Read only */
+#define LPC_SYS_AHB_CLK_CTRL_ROM        (1 <<  1)
+#define LPC_SYS_AHB_CLK_CTRL_RAM        (1 <<  2)
+#define LPC_SYS_AHB_CLK_CTRL_FLASH_REG  (1 <<  3)
+#define LPC_SYS_AHB_CLK_CTRL_FLASH      (1 <<  4)
+#define LPC_SYS_AHB_CLK_CTRL_I2C0       (1 <<  5)
+#define LPC_SYS_AHB_CLK_CTRL_GPIO       (1 <<  6)
+#define LPC_SYS_AHB_CLK_CTRL_SWM        (1 <<  7)
+#define LPC_SYS_AHB_CLK_CTRL_SCT        (1 <<  8)
+#define LPC_SYS_AHB_CLK_CTRL_WKT        (1 <<  9)
+#define LPC_SYS_AHB_CLK_CTRL_MRT        (1 << 10)
+#define LPC_SYS_AHB_CLK_CTRL_SSP0       (1 << 11)
+#define LPC_SYS_AHB_CLK_CTRL_SSP1       (1 << 12)
+#define LPC_SYS_AHB_CLK_CTRL_CRC        (1 << 13)
+#define LPC_SYS_AHB_CLK_CTRL_UART0      (1 << 14)
+#define LPC_SYS_AHB_CLK_CTRL_UART1      (1 << 15)
+#define LPC_SYS_AHB_CLK_CTRL_UART2      (1 << 16)
+#define LPC_SYS_AHB_CLK_CTRL_Watchdog   (1 << 17)
+#define LPC_SYS_AHB_CLK_CTRL_IO_CONFIG  (1 << 18)
+#define LPC_SYS_AHB_CLK_CTRL_ACMP       (1 << 19)
+#define LPC_SYS_AHB_CLK_CTRL_I2C1       (1 << 21)
+#define LPC_SYS_AHB_CLK_CTRL_I2C2       (1 << 22)
+#define LPC_SYS_AHB_CLK_CTRL_I2C3       (1 << 23)
+#define LPC_SYS_AHB_CLK_CTRL_ADC        (1 << 24)
+#define LPC_SYS_AHB_CLK_CTRL_MTB        (1 << 26)
+#define LPC_SYS_AHB_CLK_CTRL_DMA        (1 << 29)
 /* Helper */
-#define LPC_SYS_ABH_CLK_CTRL_MEM_ALL    0x0000001F
+#define LPC_SYS_AHB_CLK_CTRL_MEM_ALL    0x0000001F
 
 /* Peripheral reset */
 #define LPC_SSP0_RESET_N        (1 << 0)