git.techno-innov.fr Git - elec/adapters/prog/blob - Prog_board/Prog_board.kicad_pro

   1 {
   2   "board": {
   3     "design_settings": {
   4       "defaults": {
   5         "board_outline_line_width": 0.381,
   6         "copper_line_width": 0.381,
   7         "copper_text_italic": false,
   8         "copper_text_size_h": 1.524,
   9         "copper_text_size_v": 2.032,
  10         "copper_text_thickness": 0.30479999999999996,
  11         "copper_text_upright": false,
  12         "courtyard_line_width": 0.049999999999999996,
  13         "dimension_precision": 4,
  14         "dimension_units": 3,
  15         "dimensions": {
  16           "arrow_length": 1270000,
  17           "extension_offset": 500000,
  18           "keep_text_aligned": true,
  19           "suppress_zeroes": false,
  20           "text_position": 0,
  21           "units_format": 1
  22         },
  23         "fab_line_width": 0.09999999999999999,
  24         "fab_text_italic": false,
  25         "fab_text_size_h": 1.0,
  26         "fab_text_size_v": 1.0,
  27         "fab_text_thickness": 0.15,
  28         "fab_text_upright": false,
  29         "other_line_width": 0.09999999999999999,
  30         "other_text_italic": false,
  31         "other_text_size_h": 1.0,
  32         "other_text_size_v": 1.0,
  33         "other_text_thickness": 0.15,
  34         "other_text_upright": false,
  35         "pads": {
  36           "drill": 2.5,
  37           "height": 2.5,
  38           "width": 2.5
  39         },
  40         "silk_line_width": 0.22097999999999998,
  41         "silk_text_italic": false,
  42         "silk_text_size_h": 1.524,
  43         "silk_text_size_v": 1.524,
  44         "silk_text_thickness": 0.30479999999999996,
  45         "silk_text_upright": false,
  46         "zones": {
  47           "45_degree_only": false,
  48           "min_clearance": 0.12
  49         }
  50       },
  51       "diff_pair_dimensions": [],
  52       "drc_exclusions": [],
  53       "meta": {
  54         "filename": "board_design_settings.json",
  55         "version": 2
  56       },
  57       "rule_severities": {
  58         "annular_width": "error",
  59         "clearance": "error",
  60         "copper_edge_clearance": "error",
  61         "courtyards_overlap": "error",
  62         "diff_pair_gap_out_of_range": "error",
  63         "diff_pair_uncoupled_length_too_long": "error",
  64         "drill_out_of_range": "error",
  65         "duplicate_footprints": "warning",
  66         "extra_footprint": "warning",
  67         "footprint_type_mismatch": "error",
  68         "hole_clearance": "error",
  69         "hole_near_hole": "error",
  70         "invalid_outline": "error",
  71         "item_on_disabled_layer": "error",
  72         "items_not_allowed": "error",
  73         "length_out_of_range": "error",
  74         "malformed_courtyard": "error",
  75         "microvia_drill_out_of_range": "error",
  76         "missing_courtyard": "ignore",
  77         "missing_footprint": "warning",
  78         "net_conflict": "warning",
  79         "npth_inside_courtyard": "ignore",
  80         "padstack": "error",
  81         "pth_inside_courtyard": "ignore",
  82         "shorting_items": "error",
  83         "silk_over_copper": "warning",
  84         "silk_overlap": "warning",
  85         "skew_out_of_range": "error",
  86         "through_hole_pad_without_hole": "error",
  87         "too_many_vias": "error",
  88         "track_dangling": "warning",
  89         "track_width": "error",
  90         "tracks_crossing": "error",
  91         "unconnected_items": "error",
  92         "unresolved_variable": "error",
  93         "via_dangling": "warning",
  94         "zone_has_empty_net": "error",
  95         "zones_intersect": "error"
  96       },
  97       "rule_severitieslegacy_courtyards_overlap": true,
  98       "rule_severitieslegacy_no_courtyard_defined": false,
  99       "rules": {
 100         "allow_blind_buried_vias": false,
 101         "allow_microvias": false,
 102         "max_error": 0.005,
 103         "min_clearance": 0.0,
 104         "min_copper_edge_clearance": 0.1905,
 105         "min_hole_clearance": 0.25,
 106         "min_hole_to_hole": 0.25,
 107         "min_microvia_diameter": 0.508,
 108         "min_microvia_drill": 0.127,
 109         "min_silk_clearance": 0.0,
 110         "min_through_hole_diameter": 0.3,
 111         "min_track_width": 0.2032,
 112         "min_via_annular_width": 0.049999999999999996,
 113         "min_via_diameter": 0.508,
 114         "use_height_for_length_calcs": true
 115       },
 116       "track_widths": [],
 117       "via_dimensions": [],
 118       "zones_allow_external_fillets": false,
 119       "zones_use_no_outline": true
 120     },
 121     "layer_presets": []
 122   },
 123   "boards": [],
 124   "cvpcb": {
 125     "equivalence_files": []
 126   },
 127   "erc": {
 128     "erc_exclusions": [],
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 301     ],
 302     "rule_severities": {
 303       "bus_definition_conflict": "error",
 304       "bus_entry_needed": "error",
 305       "bus_label_syntax": "error",
 306       "bus_to_bus_conflict": "error",
 307       "bus_to_net_conflict": "error",
 308       "different_unit_footprint": "error",
 309       "different_unit_net": "error",
 310       "duplicate_reference": "error",
 311       "duplicate_sheet_names": "error",
 312       "extra_units": "error",
 313       "global_label_dangling": "warning",
 314       "hier_label_mismatch": "error",
 315       "label_dangling": "error",
 316       "lib_symbol_issues": "warning",
 317       "multiple_net_names": "warning",
 318       "net_not_bus_member": "warning",
 319       "no_connect_connected": "warning",
 320       "no_connect_dangling": "warning",
 321       "pin_not_connected": "error",
 322       "pin_not_driven": "error",
 323       "pin_to_pin": "warning",
 324       "power_pin_not_driven": "error",
 325       "similar_labels": "warning",
 326       "unannotated": "error",
 327       "unit_value_mismatch": "error",
 328       "unresolved_variable": "error",
 329       "wire_dangling": "error"
 330     }
 331   },
 332   "libraries": {
 333     "pinned_footprint_libs": [],
 334     "pinned_symbol_libs": []
 335   },
 336   "meta": {
 337     "filename": "Prog_board.kicad_pro",
 338     "version": 1
 339   },
 340   "net_settings": {
 341     "classes": [
 342       {
 343         "bus_width": 12.0,
 344         "clearance": 0.185,
 345         "diff_pair_gap": 0.25,
 346         "diff_pair_via_gap": 0.25,
 347         "diff_pair_width": 0.25,
 348         "line_style": 0,
 349         "microvia_diameter": 0.508,
 350         "microvia_drill": 0.127,
 351         "name": "Default",
 352         "pcb_color": "rgba(0, 0, 0, 0.000)",
 353         "schematic_color": "rgba(0, 0, 0, 0.000)",
 354         "track_width": 0.2032,
 355         "via_diameter": 0.508,
 356         "via_drill": 0.3,
 357         "wire_width": 6.0
 358       },
 359       {
 360         "bus_width": 12.0,
 361         "clearance": 0.19304,
 362         "diff_pair_gap": 0.25,
 363         "diff_pair_via_gap": 0.25,
 364         "diff_pair_width": 0.25,
 365         "line_style": 0,
 366         "microvia_diameter": 0.508,
 367         "microvia_drill": 0.127,
 368         "name": "HighPower",
 369         "nets": [],
 370         "pcb_color": "rgba(0, 0, 0, 0.000)",
 371         "schematic_color": "rgba(0, 0, 0, 0.000)",
 372         "track_width": 0.508,
 373         "via_diameter": 1.0,
 374         "via_drill": 0.5,
 375         "wire_width": 6.0
 376       },
 377       {
 378         "bus_width": 12.0,
 379         "clearance": 0.19304,
 380         "diff_pair_gap": 0.25,
 381         "diff_pair_via_gap": 0.25,
 382         "diff_pair_width": 0.25,
 383         "line_style": 0,
 384         "microvia_diameter": 0.508,
 385         "microvia_drill": 0.127,
 386         "name": "Power",
 387         "nets": [
 388           "/+Vsys",
 389           "/3V_prog",
 390           "/5VDebug",
 391           "/USB_5VFilt_Dbg",
 392           "/USB_5V_Dbg",
 393           "/USB_DM_Dbg",
 394           "/USB_DP_Dbg",
 395           "DGND",
 396           "GNDA"
 397         ],
 398         "pcb_color": "rgba(0, 0, 0, 0.000)",
 399         "schematic_color": "rgba(0, 0, 0, 0.000)",
 400         "track_width": 0.3,
 401         "via_diameter": 0.508,
 402         "via_drill": 0.3,
 403         "wire_width": 6.0
 404       }
 405     ],
 406     "meta": {
 407       "version": 2
 408     },
 409     "net_colors": null
 410   },
 411   "pcbnew": {
 412     "last_paths": {
 413       "gencad": "",
 414       "idf": "",
 415       "netlist": "Prog_board.net",
 416       "specctra_dsn": "",
 417       "step": "",
 418       "vrml": ""
 419     },
 420     "page_layout_descr_file": ""
 421   },
 422   "schematic": {
 423     "annotate_start_num": 0,
 424     "drawing": {
 425       "default_line_thickness": 6.0,
 426       "default_text_size": 60.0,
 427       "field_names": [],
 428       "intersheets_ref_own_page": false,
 429       "intersheets_ref_prefix": "",
 430       "intersheets_ref_short": false,
 431       "intersheets_ref_show": false,
 432       "intersheets_ref_suffix": "",
 433       "junction_size_choice": 3,
 434       "label_size_ratio": 0.25,
 435       "pin_symbol_size": 0.0,
 436       "text_offset_ratio": 0.08
 437     },
 438     "legacy_lib_dir": "",
 439     "legacy_lib_list": [],
 440     "meta": {
 441       "version": 1
 442     },
 443     "net_format_name": "Pcbnew",
 444     "ngspice": {
 445       "fix_include_paths": true,
 446       "fix_passive_vals": false,
 447       "meta": {
 448         "version": 0
 449       },
 450       "model_mode": 0,
 451       "workbook_filename": ""
 452     },
 453     "page_layout_descr_file": "../../../Lib/pagelayout.kicad_wks",
 454     "plot_directory": "",
 455     "spice_adjust_passive_values": false,
 456     "spice_external_command": "spice \"%I\"",
 457     "subpart_first_id": 65,
 458     "subpart_id_separator": 0
 459   },
 460   "sheets": [
 461     [
 462       "41bc0640-c0d0-4402-a690-7b4688197da7",
 463       ""
 464     ]
 465   ],
 466   "text_variables": {}
 467 }