git.techno-innov.fr Git - elec/adapters/prog/blob - Prog_board/Prog_board.pro

   1 update=jeu. 14 janv. 2021 23:28:49
   2 version=1
   3 last_client=kicad
   4 [cvpcb]
   5 version=1
   6 NetIExt=net
   7 [general]
   8 version=1
   9 [eeschema]
  10 version=1
  11 LibDir=
  12 [schematic_editor]
  13 version=1
  14 PageLayoutDescrFile=../../Lib/pagelayout.kicad_wks
  15 PlotDirectoryName=
  16 SubpartIdSeparator=0
  17 SubpartFirstId=65
  18 NetFmtName=Pcbnew
  19 SpiceAjustPassiveValues=0
  20 LabSize=60
  21 ERC_TestSimilarLabels=1
  22 [pcbnew]
  23 version=1
  24 PageLayoutDescrFile=
  25 LastNetListRead=Prog_board.net
  26 CopperLayerCount=2
  27 BoardThickness=1.6002
  28 AllowMicroVias=0
  29 AllowBlindVias=0
  30 RequireCourtyardDefinitions=0
  31 ProhibitOverlappingCourtyards=1
  32 MinTrackWidth=0.2032
  33 MinViaDiameter=0.508
  34 MinViaDrill=0.3
  35 MinMicroViaDiameter=0.508
  36 MinMicroViaDrill=0.127
  37 MinHoleToHole=0.25
  38 TrackWidth1=0.2032
  39 ViaDiameter1=0.508
  40 ViaDrill1=0.3
  41 dPairWidth1=0.25
  42 dPairGap1=0.25
  43 dPairViaGap1=0.25
  44 SilkLineWidth=0.22098
  45 SilkTextSizeV=1.524
  46 SilkTextSizeH=1.524
  47 SilkTextSizeThickness=0.3048
  48 SilkTextItalic=0
  49 SilkTextUpright=1
  50 CopperLineWidth=0.381
  51 CopperTextSizeV=2.032
  52 CopperTextSizeH=1.524
  53 CopperTextThickness=0.3048
  54 CopperTextItalic=0
  55 CopperTextUpright=1
  56 EdgeCutLineWidth=0.381
  57 CourtyardLineWidth=0.05
  58 OthersLineWidth=0.22098
  59 OthersTextSizeV=1
  60 OthersTextSizeH=1
  61 OthersTextSizeThickness=0.15
  62 OthersTextItalic=0
  63 OthersTextUpright=1
  64 SolderMaskClearance=0.05
  65 SolderMaskMinWidth=0.05
  66 SolderPasteClearance=-0.05
  67 SolderPasteRatio=-0
  68 [pcbnew/Layer.F.Cu]
  69 Name=Dessus
  70 Type=0
  71 Enabled=1
  72 [pcbnew/Layer.In1.Cu]
  73 Name=In1.Cu
  74 Type=0
  75 Enabled=0
  76 [pcbnew/Layer.In2.Cu]
  77 Name=In2.Cu
  78 Type=0
  79 Enabled=0
  80 [pcbnew/Layer.In3.Cu]
  81 Name=In3.Cu
  82 Type=0
  83 Enabled=0
  84 [pcbnew/Layer.In4.Cu]
  85 Name=In4.Cu
  86 Type=0
  87 Enabled=0
  88 [pcbnew/Layer.In5.Cu]
  89 Name=In5.Cu
  90 Type=0
  91 Enabled=0
  92 [pcbnew/Layer.In6.Cu]
  93 Name=In6.Cu
  94 Type=0
  95 Enabled=0
  96 [pcbnew/Layer.In7.Cu]
  97 Name=In7.Cu
  98 Type=0
  99 Enabled=0
 100 [pcbnew/Layer.In8.Cu]
 101 Name=In8.Cu
 102 Type=0
 103 Enabled=0
 104 [pcbnew/Layer.In9.Cu]
 105 Name=In9.Cu
 106 Type=0
 107 Enabled=0
 108 [pcbnew/Layer.In10.Cu]
 109 Name=In10.Cu
 110 Type=0
 111 Enabled=0
 112 [pcbnew/Layer.In11.Cu]
 113 Name=In11.Cu
 114 Type=0
 115 Enabled=0
 116 [pcbnew/Layer.In12.Cu]
 117 Name=In12.Cu
 118 Type=0
 119 Enabled=0
 120 [pcbnew/Layer.In13.Cu]
 121 Name=In13.Cu
 122 Type=0
 123 Enabled=0
 124 [pcbnew/Layer.In14.Cu]
 125 Name=In14.Cu
 126 Type=0
 127 Enabled=0
 128 [pcbnew/Layer.In15.Cu]
 129 Name=In15.Cu
 130 Type=0
 131 Enabled=0
 132 [pcbnew/Layer.In16.Cu]
 133 Name=In16.Cu
 134 Type=0
 135 Enabled=0
 136 [pcbnew/Layer.In17.Cu]
 137 Name=In17.Cu
 138 Type=0
 139 Enabled=0
 140 [pcbnew/Layer.In18.Cu]
 141 Name=In18.Cu
 142 Type=0
 143 Enabled=0
 144 [pcbnew/Layer.In19.Cu]
 145 Name=In19.Cu
 146 Type=0
 147 Enabled=0
 148 [pcbnew/Layer.In20.Cu]
 149 Name=In20.Cu
 150 Type=0
 151 Enabled=0
 152 [pcbnew/Layer.In21.Cu]
 153 Name=In21.Cu
 154 Type=0
 155 Enabled=0
 156 [pcbnew/Layer.In22.Cu]
 157 Name=In22.Cu
 158 Type=0
 159 Enabled=0
 160 [pcbnew/Layer.In23.Cu]
 161 Name=In23.Cu
 162 Type=0
 163 Enabled=0
 164 [pcbnew/Layer.In24.Cu]
 165 Name=In24.Cu
 166 Type=0
 167 Enabled=0
 168 [pcbnew/Layer.In25.Cu]
 169 Name=In25.Cu
 170 Type=0
 171 Enabled=0
 172 [pcbnew/Layer.In26.Cu]
 173 Name=In26.Cu
 174 Type=0
 175 Enabled=0
 176 [pcbnew/Layer.In27.Cu]
 177 Name=In27.Cu
 178 Type=0
 179 Enabled=0
 180 [pcbnew/Layer.In28.Cu]
 181 Name=In28.Cu
 182 Type=0
 183 Enabled=0
 184 [pcbnew/Layer.In29.Cu]
 185 Name=In29.Cu
 186 Type=0
 187 Enabled=0
 188 [pcbnew/Layer.In30.Cu]
 189 Name=In30.Cu
 190 Type=0
 191 Enabled=0
 192 [pcbnew/Layer.B.Cu]
 193 Name=Dessous
 194 Type=0
 195 Enabled=1
 196 [pcbnew/Layer.B.Adhes]
 197 Enabled=0
 198 [pcbnew/Layer.F.Adhes]
 199 Enabled=0
 200 [pcbnew/Layer.B.Paste]
 201 Enabled=0
 202 [pcbnew/Layer.F.Paste]
 203 Enabled=1
 204 [pcbnew/Layer.B.SilkS]
 205 Enabled=1
 206 [pcbnew/Layer.F.SilkS]
 207 Enabled=1
 208 [pcbnew/Layer.B.Mask]
 209 Enabled=1
 210 [pcbnew/Layer.F.Mask]
 211 Enabled=1
 212 [pcbnew/Layer.Dwgs.User]
 213 Enabled=0
 214 [pcbnew/Layer.Cmts.User]
 215 Enabled=0
 216 [pcbnew/Layer.Eco1.User]
 217 Enabled=1
 218 [pcbnew/Layer.Eco2.User]
 219 Enabled=0
 220 [pcbnew/Layer.Edge.Cuts]
 221 Enabled=1
 222 [pcbnew/Layer.Margin]
 223 Enabled=1
 224 [pcbnew/Layer.B.CrtYd]
 225 Enabled=1
 226 [pcbnew/Layer.F.CrtYd]
 227 Enabled=1
 228 [pcbnew/Layer.B.Fab]
 229 Enabled=0
 230 [pcbnew/Layer.F.Fab]
 231 Enabled=0
 232 [pcbnew/Layer.Rescue]
 233 Enabled=0
 234 [pcbnew/Netclasses]
 235 [pcbnew/Netclasses/Default]
 236 Name=Default
 237 Clearance=0.185
 238 TrackWidth=0.2032
 239 ViaDiameter=0.508
 240 ViaDrill=0.3
 241 uViaDiameter=0.508
 242 uViaDrill=0.127
 243 dPairWidth=0.25
 244 dPairGap=0.25
 245 dPairViaGap=0.25
 246 [pcbnew/Netclasses/1]
 247 Name=HighPower
 248 Clearance=0.19304
 249 TrackWidth=0.508
 250 ViaDiameter=1
 251 ViaDrill=0.5
 252 uViaDiameter=0.508
 253 uViaDrill=0.127
 254 dPairWidth=0.25
 255 dPairGap=0.25
 256 dPairViaGap=0.25
 257 [pcbnew/Netclasses/2]
 258 Name=Power
 259 Clearance=0.19304
 260 TrackWidth=0.3
 261 ViaDiameter=0.508
 262 ViaDrill=0.3
 263 uViaDiameter=0.508
 264 uViaDrill=0.127
 265 dPairWidth=0.25
 266 dPairGap=0.25
 267 dPairViaGap=0.25