git.techno-innov.fr Git - elec/adapters/prog/blob - UEXT_Cross/UEXT_Cross.kicad_pro

   1 {
   2   "board": {
   3     "design_settings": {
   4       "defaults": {
   5         "board_outline_line_width": 0.381,
   6         "copper_line_width": 0.381,
   7         "copper_text_italic": false,
   8         "copper_text_size_h": 1.524,
   9         "copper_text_size_v": 2.032,
  10         "copper_text_thickness": 0.30479999999999996,
  11         "copper_text_upright": false,
  12         "courtyard_line_width": 0.049999999999999996,
  13         "dimension_precision": 4,
  14         "dimension_units": 3,
  15         "dimensions": {
  16           "arrow_length": 1270000,
  17           "extension_offset": 500000,
  18           "keep_text_aligned": true,
  19           "suppress_zeroes": false,
  20           "text_position": 0,
  21           "units_format": 1
  22         },
  23         "fab_line_width": 0.09999999999999999,
  24         "fab_text_italic": false,
  25         "fab_text_size_h": 1.0,
  26         "fab_text_size_v": 1.0,
  27         "fab_text_thickness": 0.15,
  28         "fab_text_upright": false,
  29         "other_line_width": 0.09999999999999999,
  30         "other_text_italic": false,
  31         "other_text_size_h": 1.0,
  32         "other_text_size_v": 1.0,
  33         "other_text_thickness": 0.15,
  34         "other_text_upright": false,
  35         "pads": {
  36           "drill": 1.016,
  37           "height": 1.524,
  38           "width": 1.524
  39         },
  40         "silk_line_width": 0.29972,
  41         "silk_text_italic": false,
  42         "silk_text_size_h": 1.524,
  43         "silk_text_size_v": 1.524,
  44         "silk_text_thickness": 0.30479999999999996,
  45         "silk_text_upright": false,
  46         "zones": {
  47           "45_degree_only": false,
  48           "min_clearance": 0.2032
  49         }
  50       },
  51       "diff_pair_dimensions": [],
  52       "drc_exclusions": [],
  53       "meta": {
  54         "filename": "board_design_settings.json",
  55         "version": 2
  56       },
  57       "rule_severities": {
  58         "annular_width": "error",
  59         "clearance": "error",
  60         "copper_edge_clearance": "error",
  61         "courtyards_overlap": "error",
  62         "diff_pair_gap_out_of_range": "error",
  63         "diff_pair_uncoupled_length_too_long": "error",
  64         "drill_out_of_range": "error",
  65         "duplicate_footprints": "warning",
  66         "extra_footprint": "warning",
  67         "footprint_type_mismatch": "error",
  68         "hole_clearance": "error",
  69         "hole_near_hole": "error",
  70         "invalid_outline": "error",
  71         "item_on_disabled_layer": "error",
  72         "items_not_allowed": "error",
  73         "length_out_of_range": "error",
  74         "malformed_courtyard": "error",
  75         "microvia_drill_out_of_range": "error",
  76         "missing_courtyard": "ignore",
  77         "missing_footprint": "warning",
  78         "net_conflict": "warning",
  79         "npth_inside_courtyard": "ignore",
  80         "padstack": "error",
  81         "pth_inside_courtyard": "ignore",
  82         "shorting_items": "error",
  83         "silk_over_copper": "warning",
  84         "silk_overlap": "warning",
  85         "skew_out_of_range": "error",
  86         "through_hole_pad_without_hole": "error",
  87         "too_many_vias": "error",
  88         "track_dangling": "warning",
  89         "track_width": "error",
  90         "tracks_crossing": "error",
  91         "unconnected_items": "error",
  92         "unresolved_variable": "error",
  93         "via_dangling": "warning",
  94         "zone_has_empty_net": "error",
  95         "zones_intersect": "error"
  96       },
  97       "rules": {
  98         "allow_blind_buried_vias": false,
  99         "allow_microvias": false,
 100         "max_error": 0.005,
 101         "min_clearance": 0.0,
 102         "min_copper_edge_clearance": 0.1905,
 103         "min_hole_clearance": 0.25,
 104         "min_hole_to_hole": 0.25,
 105         "min_microvia_diameter": 0.508,
 106         "min_microvia_drill": 0.127,
 107         "min_silk_clearance": 0.0,
 108         "min_through_hole_diameter": 0.3,
 109         "min_track_width": 0.2032,
 110         "min_via_annular_width": 0.049999999999999996,
 111         "min_via_diameter": 0.508,
 112         "use_height_for_length_calcs": true
 113       },
 114       "track_widths": [],
 115       "via_dimensions": [],
 116       "zones_allow_external_fillets": false,
 117       "zones_use_no_outline": true
 118     },
 119     "layer_presets": []
 120   },
 121   "boards": [],
 122   "cvpcb": {
 123     "equivalence_files": []
 124   },
 125   "erc": {
 126     "erc_exclusions": [],
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 299     ],
 300     "rule_severities": {
 301       "bus_definition_conflict": "error",
 302       "bus_entry_needed": "error",
 303       "bus_label_syntax": "error",
 304       "bus_to_bus_conflict": "error",
 305       "bus_to_net_conflict": "error",
 306       "different_unit_footprint": "error",
 307       "different_unit_net": "error",
 308       "duplicate_reference": "error",
 309       "duplicate_sheet_names": "error",
 310       "extra_units": "error",
 311       "global_label_dangling": "warning",
 312       "hier_label_mismatch": "error",
 313       "label_dangling": "error",
 314       "lib_symbol_issues": "warning",
 315       "multiple_net_names": "warning",
 316       "net_not_bus_member": "warning",
 317       "no_connect_connected": "warning",
 318       "no_connect_dangling": "warning",
 319       "pin_not_connected": "error",
 320       "pin_not_driven": "error",
 321       "pin_to_pin": "warning",
 322       "power_pin_not_driven": "error",
 323       "similar_labels": "warning",
 324       "unannotated": "error",
 325       "unit_value_mismatch": "error",
 326       "unresolved_variable": "error",
 327       "wire_dangling": "error"
 328     }
 329   },
 330   "libraries": {
 331     "pinned_footprint_libs": [],
 332     "pinned_symbol_libs": []
 333   },
 334   "meta": {
 335     "filename": "UEXT_Cross.kicad_pro",
 336     "version": 1
 337   },
 338   "net_settings": {
 339     "classes": [
 340       {
 341         "bus_width": 12.0,
 342         "clearance": 0.19304,
 343         "diff_pair_gap": 0.25,
 344         "diff_pair_via_gap": 0.25,
 345         "diff_pair_width": 0.2,
 346         "line_style": 0,
 347         "microvia_diameter": 0.508,
 348         "microvia_drill": 0.127,
 349         "name": "Default",
 350         "pcb_color": "rgba(0, 0, 0, 0.000)",
 351         "schematic_color": "rgba(0, 0, 0, 0.000)",
 352         "track_width": 0.2032,
 353         "via_diameter": 0.508,
 354         "via_drill": 0.3,
 355         "wire_width": 6.0
 356       },
 357       {
 358         "bus_width": 12.0,
 359         "clearance": 0.19304,
 360         "diff_pair_gap": 0.25,
 361         "diff_pair_via_gap": 0.25,
 362         "diff_pair_width": 0.2,
 363         "line_style": 0,
 364         "microvia_diameter": 0.508,
 365         "microvia_drill": 0.127,
 366         "name": "Alim3.3",
 367         "nets": [
 368           "+3.3V",
 369           "DGND"
 370         ],
 371         "pcb_color": "rgba(0, 0, 0, 0.000)",
 372         "schematic_color": "rgba(0, 0, 0, 0.000)",
 373         "track_width": 0.3048,
 374         "via_diameter": 0.889,
 375         "via_drill": 0.508,
 376         "wire_width": 6.0
 377       },
 378       {
 379         "bus_width": 12.0,
 380         "clearance": 0.15,
 381         "diff_pair_gap": 0.25,
 382         "diff_pair_via_gap": 0.25,
 383         "diff_pair_width": 0.2,
 384         "line_style": 0,
 385         "microvia_diameter": 0.508,
 386         "microvia_drill": 0.127,
 387         "name": "USBSignal",
 388         "nets": [],
 389         "pcb_color": "rgba(0, 0, 0, 0.000)",
 390         "schematic_color": "rgba(0, 0, 0, 0.000)",
 391         "track_width": 0.4,
 392         "via_diameter": 0.508,
 393         "via_drill": 0.3,
 394         "wire_width": 6.0
 395       }
 396     ],
 397     "meta": {
 398       "version": 2
 399     },
 400     "net_colors": null
 401   },
 402   "pcbnew": {
 403     "last_paths": {
 404       "gencad": "",
 405       "idf": "",
 406       "netlist": "UEXT_Cross.net",
 407       "specctra_dsn": "",
 408       "step": "",
 409       "vrml": ""
 410     },
 411     "page_layout_descr_file": "${KICAD7_TEMPLATE_DIR}/pagelayout.kicad_wks"
 412   },
 413   "schematic": {
 414     "annotate_start_num": 0,
 415     "drawing": {
 416       "default_line_thickness": 6.0,
 417       "default_text_size": 60.0,
 418       "field_names": [],
 419       "intersheets_ref_own_page": false,
 420       "intersheets_ref_prefix": "",
 421       "intersheets_ref_short": false,
 422       "intersheets_ref_show": false,
 423       "intersheets_ref_suffix": "",
 424       "junction_size_choice": 3,
 425       "label_size_ratio": 0.25,
 426       "pin_symbol_size": 0.0,
 427       "text_offset_ratio": 0.08
 428     },
 429     "legacy_lib_dir": "",
 430     "legacy_lib_list": [],
 431     "meta": {
 432       "version": 1
 433     },
 434     "net_format_name": "",
 435     "ngspice": {
 436       "fix_include_paths": true,
 437       "fix_passive_vals": false,
 438       "meta": {
 439         "version": 0
 440       },
 441       "model_mode": 0,
 442       "workbook_filename": ""
 443     },
 444     "page_layout_descr_file": "../../../Lib/pagelayout.kicad_wks",
 445     "plot_directory": "",
 446     "spice_adjust_passive_values": false,
 447     "spice_external_command": "spice \"%I\"",
 448     "subpart_first_id": 65,
 449     "subpart_id_separator": 0
 450   },
 451   "sheets": [
 452     [
 453       "cf42c984-ff03-4b25-8f8f-b8b0df44c045",
 454       ""
 455     ]
 456   ],
 457   "text_variables": {}
 458 }